US 12,287,984 B2
Data processing system and method for accessing heterogeneous memory system including processing unit
Wonseb Jeong, Suwon-si (KR); Hongju Kal, Seoul (KR); Won Woo Ro, Seoul (KR); Seokmin Lee, Goryeong-gun (KR); and Gun Ko, Gunpo-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, Seoul (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 6, 2023, as Appl. No. 18/531,094.
Application 18/531,094 is a continuation of application No. 17/837,286, filed on Jun. 10, 2022, granted, now 11,880,590.
Claims priority of application No. 10-2021-0075745 (KR), filed on Jun. 10, 2021; and application No. 10-2021-0117942 (KR), filed on Sep. 3, 2021.
Prior Publication US 2024/0103755 A1, Mar. 28, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory module configured to store first data;
a high bandwidth memory (HBM) configured to store second data, the HBM comprising a plurality of memory dies arranged in a stacked form, and each plurality of memory dies including a processing-in-memory (PIM) circuit configured to perform an arithmetic operation; and
a memory controller configured to:
detect a data array from the memory module or the HBM based on a border index value that indicates which memory, among the memory module and the HBM, stores the data array required for the arithmetic operation of the PIM circuit, and generate a memory module command set based on a first physical address space corresponding to the memory module or a HBM command set based on a second physical address space corresponding to the HBM in relation to the data array.