US 12,287,844 B1
Matrix multiplication hardware architecture
Shulin Zeng, Shanghai (CN); Shengen Yan, Shanghai (CN); Jintao Li, Shanghai (CN); Yadong Dai, Shanghai (CN); and Kairui Wen, Shanghai (CN)
Assigned to SHANGHAI INFINIGENCE AI INTELLIGENT TECHNOLOGY CO., LTD., Shanghai (CN)
Filed by SHANGHAI INFINIGENCE AI INTELLIGENT TECHNOLOGY CO., LTD., Shanghai (CN)
Filed on Sep. 25, 2024, as Appl. No. 18/896,556.
Claims priority of application No. 202311738376.8 (CN), filed on Dec. 18, 2023.
Int. Cl. G06F 17/16 (2006.01); G06F 15/80 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 15/8053 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A matrix multiplication hardware architecture, comprising:
a reduction network, comprising a tree topology with multiple levels formed by a plurality of reduction network nodes, wherein the reduction network node comprises a data selector and two computation paths; and
a digital signal processing unit DSP48 chain, formed by cascading a plurality of digital signal processing units DSP48, wherein output ends of two adjacent digital signal processing units DSP48 are respectively connected to two computation paths of a same reduction network node in a first level of the tree topology, and outputs of two computation paths pass through a data selector and then are connected to a reduction network node in an upper level of the tree topology,
wherein a pre-adder and a post-adder are arranged inside the digital signal processing unit DSP48, wherein a plurality of sets of logic circuits are arranged on an input side and an output side of the pre-adder, and a plurality of sets of logic circuits are arranged on an input side and an output side of the post-adder.