| CPC G06F 13/4221 (2013.01) [G06F 12/0238 (2013.01); G06F 13/1668 (2013.01)] | 20 Claims |
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1. A computing system comprising:
a first storage device;
a second storage device;
a memory device comprising a processor, a buffer memory interface circuit and a buffer memory, the processor of the memory device being configured to store first map data of the first storage device and second map data of the second storage device; and
a compute express link (CXL) switch connected with the first storage device, the second storage device, and an external host through a first interface, and configured to arbitrate communications between the first storage device, the second storage device, and the external host,
wherein the first storage device is connected with the memory device through a second interface,
wherein the second storage device is connected with the memory device through a third interface,
wherein the first interface, the second interface, and the third interface are physically separated from each other,
wherein, in an initialization operation, the processor of the memory device allocates at least a first partial area of the buffer memory as a first dedicated area for storing the first map data of the first storage device, and
wherein, in the initialization operation, the processor of the memory device allocates at least a second partial area of the buffer memory as a second dedicated area for storing the second map data of the second storage device.
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