US 12,287,748 B2
High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection
Xiaojie Ma, Wuxi (CN); Yanfeng Xu, Wuxi (CN); Yuting Xu, Wuxi (CN); Boyin Chen, Wuxi (CN); Yanfei Zhang, Wuxi (CN); and Yueer Shan, Wuxi (CN)
Assigned to WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed by WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed on Aug. 9, 2023, as Appl. No. 18/446,501.
Application 18/446,501 is a continuation in part of application No. PCT/CN2023/082961, filed on Mar. 22, 2023.
Claims priority of application No. 202211730093.4 (CN), filed on Dec. 30, 2022.
Prior Publication US 2023/0385222 A1, Nov. 30, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 11/27 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 11/27 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A high-speed low-latency interconnect interface (HLII) for a silicon interposer interconnection, comprising a physical layer (PL) and a link layer (LL) between a logical resource inside a chiplet and the PL, wherein
the LL is configured to receive a signal of the logical resource inside the chiplet, transmit the signal of the logical resource inside the chiplet to the PL, and the LL is further configured to control the PL based on the signal of the logical resource inside the chiplet, wherein the signal of the logical resource inside the chiplet comprises a data signal, and the operation of transmitting, by the LL, the signal of the logical resource inside the chiplet to the PL comprises performing data conversion on the data signal to obtain a converted data signal and sending the converted data signal to the PL; and
the PL is configured to receive the signal transmitted through the LL, and transmit the signal to a PL of another HLII through a silicon interposer; and the PL is further configured to receive a signal transmitted by the PL of the another HLII, and transmit the signal transmitted by the PL of the another HLII to the LL of the HLII, wherein the LL receives the signal and transmits the signal to the logical resource inside the chiplet;
wherein the PL comprises at least one transmission channel, and the LL comprises at least one logical control channel, wherein a quantity of transmission channels is the same as a quantity of logical control channels;
each of the transmission channels is configured to transmit the data signal, and modes of transmitting, by the transmission channels, the data signal comprise a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode;
each of the logical control channels is configured to control and schedule a data flow transmitted by corresponding one transmission channel;
each of the transmission channels comprises a plurality of transmission subchannels, and each of the plurality of transmission subchannels is responsible for transmitting at least a 32-bit data signal; and
each of the logical control channels comprises a plurality of logical control subchannels, the plurality of logical control subchannels are in one-to-one correspondence with the plurality of transmission subchannels, and each of the plurality of logical control subchannels is configured to control and schedule a data flow transmitted by corresponding one transmission subchannel.