US 12,287,739 B2
Accessing a cache based on an address translation buffer result
Jagadish B Kotra, Austin, TX (US); and John Kalamatianos, Arlington, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 9, 2022, as Appl. No. 18/064,155.
Prior Publication US 2024/0193097 A1, Jun. 13, 2024
Int. Cl. G06F 12/1045 (2016.01); G06F 12/0888 (2016.01); G06F 12/0897 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/1045 (2013.01) [G06F 12/0888 (2013.01); G06F 12/0897 (2013.01); G06F 12/1027 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a memory request targeting a virtual address;
in response to a translation lookaside buffer miss, translating the virtual address to a physical address via a page walk; and
in response to a translation response indicating the translation lookaside buffer miss, bypassing a first level of a cache, accessing a second level of the cache, and allocating a miss status handling register at the first level of the cache.