US 12,287,729 B2
Neural processing device and method for transmitting data thereof
Sungpill Choi, Seongnam-si (KR); and Jae-Sung Yoon, Seongnam-si (KR)
Assigned to Rebellions Inc., Seongnam-si (KR)
Filed by Rebellions Inc., Seongnam-si (KR)
Filed on Mar. 7, 2024, as Appl. No. 18/599,031.
Application 18/599,031 is a continuation of application No. 18/366,627, filed on Aug. 7, 2023, granted, now 11,960,391.
Claims priority of application No. 10-2022-0118173 (KR), filed on Sep. 19, 2022.
Prior Publication US 2024/0211389 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 12/084 (2016.01); G06N 3/063 (2023.01)
CPC G06F 12/023 (2013.01) [G06F 12/084 (2013.01); G06N 3/063 (2013.01); G06F 2212/1016 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A processing device comprising processing circuitry comprising:
a plurality of processors;
a first memory shared by the plurality of processors; and
a cache comprising a second memory comprising a plurality of memory units, each of the plurality of memory units in the second memory being associated with a respective one of a plurality of request identifiers,
wherein the cache is configured to cause:
receiving, from at least one of the plurality of processors, a memory read request including a request identifier and a memory address,
identifying an allocated memory address identifier for the memory address,
accessing the first memory to read data of the memory address,
obtaining one or more request identifiers which requested data of the memory address from the second memory based on the allocated memory address identifier, and
transmitting the data of the memory address to one or more processors which requested data of the memory address based on the one or more request identifiers,
wherein the cache further comprises:
a third memory including a plurality of memory units, each of the plurality of memory units in the third memory being associated with a respective one of a plurality of memory address identifiers,
wherein the cache is further configured to cause:
reading a memory unit of the third memory based on the allocated memory address identifier to obtain a tail request identifier,
storing the request identifier of the memory read request to a memory unit of the second memory based on the tail request identifier, and
writing the request identifier of the memory read request as the tail request identifier to a memory unit of the third memory based on the allocated memory address identifier.