US 12,287,705 B2
Memory device and repair method with column-based error code tracking
Frederick A. Ware, Los Altos Hills, CA (US); and Brent Steven Haukness, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Feb. 16, 2024, as Appl. No. 18/444,320.
Application 18/444,320 is a continuation of application No. 17/548,509, filed on Dec. 11, 2021, granted, now 11,921,576.
Application 17/548,509 is a continuation of application No. 16/790,637, filed on Feb. 13, 2020, granted, now 11,204,825, issued on Dec. 21, 2021.
Application 16/790,637 is a continuation of application No. 15/646,025, filed on Jul. 10, 2017, granted, now 10,565,049, issued on Feb. 18, 2020.
Application 15/646,025 is a continuation of application No. 14/458,546, filed on Aug. 13, 2014, granted, now 9,715,424, issued on Jul. 25, 2017.
Claims priority of provisional application 61/869,325, filed on Aug. 23, 2013.
Prior Publication US 2024/0272980 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 12/02 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1008 (2013.01) [G06F 11/1048 (2013.01); G06F 12/0246 (2013.01); G11C 29/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device, comprising:
DRAM memory core circuitry including multiple rows of data storage locations and error storage locations;
DRAM memory interface circuitry to receive a read command to activate a given row of the multiple rows of data storage locations and error storage locations;
register storage; and
repair circuitry, responsive to the read command, to access error information from the error storage locations of the activated given row and to store the error information in the register storage, the error information used to generate a comparison result for a repair operation.