US 12,287,553 B2
Array substrate and display device
Wenpeng Ma, Beijing (CN); Yinlong Zhang, Beijing (CN); Zhihua Sun, Beijing (CN); Shulin Yao, Beijing (CN); Pengfei Hu, Beijing (CN); Qi Li, Beijing (CN); Xibin Shao, Beijing (CN); and Yanping Liao, Beijing (CN)
Assigned to BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Chaoyang (CN)
Appl. No. 17/758,334
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Sep. 10, 2021, PCT No. PCT/CN2021/117701
§ 371(c)(1), (2) Date Jul. 1, 2022,
PCT Pub. No. WO2022/083347, PCT Pub. Date Apr. 28, 2022.
Claims priority of application No. 202011147010.X (CN), filed on Oct. 23, 2020.
Prior Publication US 2023/0037762 A1, Feb. 9, 2023
Int. Cl. G02F 1/1362 (2006.01); G02F 1/133 (2006.01); G02F 1/1345 (2006.01); G09G 3/20 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G02F 1/136286 (2013.01) [G02F 1/13306 (2013.01); G02F 1/13452 (2013.01); G09G 3/2096 (2013.01); G09G 2300/0413 (2013.01); G09G 2310/0297 (2013.01); G09G 2320/043 (2013.01); H10D 86/443 (2025.01); H10D 86/60 (2025.01)] 14 Claims
OG exemplary drawing
 
1. An array substrate, comprising a plurality of gate lines and a plurality of data lines arranged in a crosswise manner to define a plurality of subpixels in an array form, wherein
the plurality of subpixels is arranged in N columns, and the subpixels in each column are arranged in a first direction, where N is a positive integer;
the plurality of data lines comprises one start data line, N−1 intermediate data lines and one end data line, the start data line is electrically coupled to target subpixels in sub-pixels in a first column, the N−1 intermediate data lines correspond to the subpixels in the first to (N−1)th columns respectively, each intermediate data line is electrically coupled to non-target subpixels in subpixels in a corresponding column and target subpixels in subpixels of a next column adjacent to the corresponding column, the end data line is electrically coupled to non-target subpixels in sub-pixels of an Nth column, the target subpixels are ones of odd-numbered subpixels and even-numbered subpixels, and the non-target subpixels are the other ones of the odd-numbered subpixels and the even-numbered subpixels; and
the array substrate further comprises a first driving circuit and a second driving circuit, the first driving circuit is arranged at a first side of the plurality of data lines, the second driving circuit is arranged at a second side of the plurality of data lines, the first side is opposite to the second side in the first direction, the first driving circuit is electrically coupled to a first end of each of the plurality of data lines, a first end of the end data line is electrically coupled to a first end of the start data line, and the second driving circuit is electrically coupled to a second end of each of the plurality of data lines;
the array substrate further comprises a first circuit board arranged at the first side and provided with a first connection line, wherein the first connection line is electrically coupled to the first end of the start data line and the first end of the end data line;
wherein a second end of the end data line is electrically coupled to a second end of the start data line;
the array substrate further comprises a second circuit board arranged at the second side and provided with a second connection line, wherein the second connection line is electrically coupled to the second end of the start data line and the second end of the end data line;
wherein the first circuit board comprises a plurality of first circuit sub-boards spliced together and arranged sequentially in a second direction, the second direction intersects the first direction, and the first connection line comprises a plurality of first connection sub-lines arranged on the first circuit sub-boards respectively and electrically coupled to each other in an end-to-end manner; and/or
the second circuit board comprises a plurality of second circuit sub-boards spliced together and arranged sequentially in the second direction, and the second connection line comprises a plurality of second connection sub-lines arranged on the second circuit sub-boards respectively and electrically coupled to each other in an end-to-end manner.