US 12,287,540 B2
Array substrate and method for manufacturing same, and liquid crystal panel
Ting Wan, Beijing (CN); Ruifang Du, Beijing (CN); Chengyong Zhan, Beijing (CN); Na Sui, Beijing (CN); and Yanlong Li, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/282,984
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Aug. 31, 2022, PCT No. PCT/CN2022/116330
§ 371(c)(1), (2) Date Sep. 19, 2023,
PCT Pub. No. WO2024/045076, PCT Pub. Date Mar. 7, 2024.
Prior Publication US 2025/0035972 A1, Jan. 30, 2025
Int. Cl. G02F 1/1333 (2006.01); G02F 1/1339 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC G02F 1/133345 (2013.01) [G02F 1/13394 (2013.01); G02F 1/136227 (2013.01); G02F 1/1368 (2013.01); H01L 27/1248 (2013.01); G02F 1/133305 (2013.01); G02F 1/13439 (2013.01); H01L 27/124 (2013.01)] 20 Claims
OG exemplary drawing
 
19. A liquid crystal panel, comprising: an array substrate and a cover plate that are opposite, and a liquid crystal layer between the array substrate and the cover plate, wherein the array substrate is provided with a display region and a non-display region on a periphery of the display region, and comprises:
a base substrate;
a pixel electrode and a thin-film transistor on a side of the base substrate, wherein the pixel electrode and the thin-film transistor are disposed in the display region, and the pixel electrode is disposed on a side, facing away from the base substrate, of the thin-film transistor;
a first passivation layer between the pixel electrode and the thin-film transistor, wherein a plurality of first vias are defined in the first passivation layer, at least part of the plurality of first vias are disposed in the display region, and the pixel electrode is electrically connected to the thin-film transistor through the at least part of the plurality of first vias in the display region; and
a second passivation layer on a side, facing away from the base substrate, of the pixel electrode, wherein a plurality of second vias are defined in the second passivation layer, at least part of the plurality of second vias are disposed in the display region, the at least part of the plurality of second vias in the display region are in one-to-one correspondence to the at least part of the plurality of first vias in the display region, and an overlapped region is present between an orthogonal projection of each of the at least part of the plurality of second vias in the display region on the base substrate and an orthogonal projection of the corresponding first via on the base substrate.