US 12,287,369 B1
Self-correcting circuitry
Patrick Murphy, Cork (IE); Cornelius O'Shea, Cork (IE); Joe Canning, Cork (IE); Dariusz Piotr Palubiak, Cork (IE); and Vitali Karasenko, Cork (IE)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 2, 2023, as Appl. No. 18/364,064.
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318525 (2013.01) [G01R 31/318572 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first self-correcting latch circuit including a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs, wherein each of the plurality of memory loops is configured to store data in parallel, wherein the first self-correcting latch circuit includes voting logic configured to receive the plurality of outputs to reject any error in the plurality of memory loops, wherein the voting logic of the first self-correcting latch circuit is implemented in lockstep at the end of a logic chain.