US 12,287,356 B2
Voltage hold circuit, voltage monitoring circuit, and semiconductor integrated circuit
Kengo Komiya, Yokohama (JP); Akimitsu Tajima, Yokohama (JP); and Takeshi Kimura, Yokohama (JP)
Assigned to SOCIONEXT INC., Yokohama (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on May 17, 2022, as Appl. No. 17/746,467.
Application 17/746,467 is a continuation of application No. PCT/JP2019/046716, filed on Nov. 29, 2019.
Prior Publication US 2022/0276286 A1, Sep. 1, 2022
Int. Cl. G01R 19/04 (2006.01); G01R 19/25 (2006.01); G05F 1/46 (2006.01)
CPC G01R 19/04 (2013.01) [G01R 19/2503 (2013.01); G05F 1/468 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit comprising:
a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every processing cycle, by using a first capacitor and a first comparator to compare the input voltage signal with a minimum voltage held in the first capacitor; and
a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every processing cycle, by using a second capacitor and a second comparator to compare the input voltage signal with a maximum voltage held in the second capacitor.