| CPC C23C 14/568 (2013.01) [C23C 14/081 (2013.01); C23C 16/403 (2013.01); C23C 16/54 (2013.01); H01L 21/67184 (2013.01); H10N 50/01 (2023.02)] | 11 Claims |
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1. An apparatus for manufacturing a semiconductor device, the apparatus comprising:
process chambers arranged in a first row and a second row, all the process chambers being in the first and second rows, and the process chambers including:
a first process chamber, a second process chamber, and a third process chamber arranged in the first row in a first direction; and
a fourth process chamber, a fifth process chamber, and a sixth process chamber arranged in the second row in the first direction, the fourth process chamber, the fifth process chamber, and the sixth process chamber being spaced apart from the first process chamber, the second process chamber, and the third process chamber, respectively, in a second direction intersecting the first direction,
wherein the first process chamber is configured to deposit a first magnetic layer of a magnetic memory element,
wherein the second process chamber and the fifth process chamber are configured to perform a first same process to deposit a tunnel barrier of the magnetic memory element,
wherein the third process chamber and the sixth process chamber are configured to perform a second same process to deposit a second magnetic layer of the magnetic memory element, and
wherein the fourth process chamber is configured to deposit a capping layer of the magnetic memory element;
at least one load-lock chamber at one side of the first to sixth process chambers in the first direction, the at least one load-lock chamber configured to receive a semiconductor substrate transferred to the first to sixth process chambers or transferred from the first to sixth process chambers;
transfer chambers arranged between the first row and the second row, all the transfer chambers being between the first and second rows, and the transfer chambers including:
a first transfer chamber, a second transfer chamber, and a third transfer chamber arranged in a third row in the first direction, the third row being between the first row and the second row,
wherein the first transfer chamber is directly connected to the second transfer chamber, the at least one load-lock chamber, the first process chamber, and the fourth process chamber,
wherein the second transfer chamber is directly connected to the third transfer chamber, the first process chamber, the second process chamber, the fourth process chamber, and the fifth process chamber,
wherein the third transfer chamber is directly connected to the second process chamber, the third process chamber, the fifth process chamber, and the sixth process chamber; and
a controller configured to control the apparatus to, in order:
carry the semiconductor substrate from the at least one load-lock chamber to the first transfer chamber and from the first transfer chamber to the first process chamber,
in the first process chamber, deposit the first magnetic layer of the magnetic memory element on the semiconductor substrate,
carry the semiconductor substrate from the first process chamber to the second transfer chamber and from the second transfer chamber to the second process chamber,
in the second process chamber, deposit the tunnel barrier of the magnetic memory element on the semiconductor substrate,
carry the semiconductor substrate from the second process chamber to the third transfer chamber and from the third transfer chamber to the third process chamber,
in the third process chamber, deposit the second magnetic layer of the magnetic memory element on the semiconductor substrate,
carry the semiconductor substrate to the fourth process chamber,
in the fourth process chamber, deposit the capping layer of the magnetic memory element on the semiconductor substrate, and
transfer the semiconductor substrate from the fourth process chamber to the first transfer chamber and from the first transfer chamber to the at least one load-lock chamber.
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