US 12,284,922 B2
Stacked access device and resistive memory
Hiroyuki Miyazoe, White Plains, NY (US); Gloria W. Y. Fraczak, Bayside, NY (US); Kumar R. Virwani, Santa Clara, CA (US); and Takashi Ando, Eastchester, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Feb. 24, 2022, as Appl. No. 17/679,418.
Application 17/679,418 is a division of application No. 16/291,177, filed on Mar. 4, 2019, granted, now 11,289,650.
Prior Publication US 2022/0181550 A1, Jun. 9, 2022
Int. Cl. H01L 45/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/011 (2023.02) [H10B 63/24 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method comprising:
forming a bottom electrode layer over a substrate;
forming a mixed ionic-electronic conductor (MIEC) layer including copper, germanium, and sulfur in direct contact with the bottom electrode layer
forming a middle electrode layer over the MIEC layer;
forming a metal oxide layer over the middle electrode layer;
forming a first top electrode layer and a second top electrode layer over the metal oxide layer, the first top electrode layer, the second top electrode layer, and the metal oxide layer forming a stack; and forming sidewall spacers on sidewalls of the stack such that the sidewall spacers are positioned directly in contact with a surface of the middle electrode layer, and, in their entirety, over the surface of the middle electrode layer.