US 12,284,890 B2
Display panel
Ziyang Yu, Beijing (CN); and Qian Li, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/764,479
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jun. 25, 2021, PCT No. PCT/CN2021/102249
§ 371(c)(1), (2) Date Mar. 28, 2022,
PCT Pub. No. WO2022/266979, PCT Pub. Date Dec. 29, 2022.
Prior Publication US 2023/0263020 A1, Aug. 17, 2023
Int. Cl. G09G 3/3208 (2016.01); G09G 3/3233 (2016.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); H10K 59/124 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2330/028 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit;
wherein the display panel comprises:
a plurality of light emitting elements; and
an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements;
wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area;
the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer;
the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer; and
the plurality of first signal lines are electrically connected to the plurality of second signal lines;
wherein the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines interconnect through first vias respectively extending through the planarization layer, at least some of the first vias being in the display area;
a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines respectively through multiple first vias extending through the planarization layer; and
a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines respectively through multiple first vias extending through the planarization layer.