US 12,284,882 B2
Array substrate with shielding structure and manufacturing method thereof, display panel and display device
Gang Wang, Beijing (CN); Kai Zhang, Beijing (CN); Tsanghong Wang, Beijing (CN); Erlong Song, Beijing (CN); and Xingrui Cai, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/419,389
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 22, 2020, PCT No. PCT/CN2020/116915
§ 371(c)(1), (2) Date Jun. 29, 2021,
PCT Pub. No. WO2022/061546, PCT Pub. Date Mar. 31, 2022.
Prior Publication US 2022/0320221 A1, Oct. 6, 2022
Int. Cl. H10K 59/126 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/126 (2023.02) [H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 12 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate;
a first metal layer, arranged on the substrate and comprising a luminous control signal line;
a second metal layer, arranged on one side, departing from the substrate of the first metal layer and comprising an anode overlap electrode; wherein the anode overlap electrode and the luminous control signal line have a first overlapping area; and
a shielding structure, arranged between the first metal layer and the second metal layer and mutually insulated from the first metal layer and the second metal layer;
wherein an orthographic projection of the shielding structure on the substrate at least partially covers an orthographic projection of the first overlapping area on the substrate; and
the shielding structure is coupled to a fixed potential;
wherein the array substrate further comprises: a third metal layer arranged between the first metal layer and the second metal layer; wherein the shielding structure is arranged on the third metal layer;
wherein the second metal layer further comprises a drive voltage signal line; the third metal layer comprises a capacitor plate electrically connected with the drive voltage signal line; and the shielding structure and the capacitor plate are an integral structure;
or,
wherein the third metal layer further comprises an initialization signal line; and the shielding structure and the initialization signal line are an integral structure.