US 12,284,876 B2
Array substrate and display panel
Huihui Zhao, Hubei (CN); and Hao Peng, Hubei (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Wuhan (CN)
Filed by WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD., Hubei (CN)
Filed on Mar. 31, 2024, as Appl. No. 18/622,981.
Application 18/622,981 is a continuation of application No. 17/261,029, granted, now 11,997,877, previously published as PCT/CN2020/111420, filed on Aug. 26, 2020.
Claims priority of application No. 202010671364.8 (CN), filed on Jul. 13, 2020.
Prior Publication US 2024/0244884 A1, Jul. 18, 2024
Int. Cl. H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate;
a polysilicon active layer disposed at a side of the substrate;
a first metal layer disposed at a side of the polysilicon active layer away from the substrate;
an oxide active layer disposed at a side of the first metal layer away from the substrate;
a third metal layer disposed at a side of the oxide active layer away from the substrate; and
a source/drain layer disposed at a side of the third metal layer away from the substrate;
wherein the first metal layer is patterned to form a first gate electrode of a low temperature polysilicon thin film transistor, the source/drain layer is patterned to form a first source electrode and a first drain electrode of the low temperature polysilicon thin film transistor, and the first source electrode and the first drain electrode are connected to the polysilicon active layer;
wherein the third metal layer is patterned to form a second gate electrode of a low temperature polycrystalline oxide thin film transistor, and the source/drain layer is further patterned to form a second source electrode and a second drain electrode of the low temperature polycrystalline oxide thin film transistor, and the second source electrode and the second drain electrode are connected to the oxide active layer;
wherein the second source electrode is directly connected to the polysilicon active layer through a through hole;
wherein the array substrate further comprises a first interlayer dielectric layer disposed between the first metal layer and the oxide active layer; and
wherein the through hole has a stair at the first interlayer dielectric layer and has a taper angle of 40° to 80°, and an edge of the stair is smooth.