US 12,284,872 B2
Display panel and preparation method thereof, and display device
Yong Yuan, Xiamen (CN); Shui He, Xiamen (CN); and Feng Xie, Xiamen (CN)
Assigned to XIAMEN TIANMA MICROELECTRONICS CO., LTD., Xiamen (CN)
Filed by Xiamen Tianma Microelectronics Co., Ltd., Xiamen (CN)
Filed on Dec. 14, 2021, as Appl. No. 17/550,732.
Claims priority of application No. 202110574112.8 (CN), filed on May 25, 2021.
Prior Publication US 2022/0109037 A1, Apr. 7, 2022
Int. Cl. H01L 27/14 (2006.01); G09G 3/3233 (2016.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01); H10K 77/10 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10K 59/12 (2023.01); H10K 102/00 (2023.01)
CPC H10K 59/1213 (2023.02) [G09G 3/3233 (2013.01); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H10K 77/111 (2023.02); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1251 (2013.01); H01L 29/78675 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10K 59/1201 (2023.02); H10K 2102/311 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a base substrate;
a first transistor, wherein the first transistor comprises a first active layer, a first gate, a first source, and a first drain, wherein the first active layer contains silicon;
a second transistor, wherein the second transistor comprises a second active layer, a second gate, a second source, and a second drain, wherein the second active layer contains silicon;
a third transistor, wherein the third transistor comprises a third active layer, a third gate, a third source, and a third drain, wherein the third active layer contains an oxide semiconductor;
a pixel circuit, wherein the pixel circuit supplies a drive current to a display element of the display panel; and
a driver circuit, wherein the driver circuit supplies a drive signal to the pixel circuit; wherein
the driver circuit comprises the first transistor, and the pixel circuit comprises the second transistor and the third transistor; and
a subthreshold swing of the first transistor is SS1, and a subthreshold swing of the second transistor is SS2, wherein SS1<SS2;
the first transistor comprises a first insulating layer, wherein the first insulating layer is located between the first source or the first drain and the first active layer, and the first insulating layer extends to the second transistor and is located between the second source and the second active layer or between the second drain and the second active layer;
wherein the first insulating layer is located in a first area in the first transistor, the first insulating layer is located in a second area in the second transistor, and a hydrogen concentration in the first area is higher than a hydrogen concentration in the second area.