US 12,284,834 B2
Semiconductor devices and methods of manufacturing semiconductor devices
Derrick Johnson, Phoenix, AZ (US); Yupeng Chen, San Jose, CA (US); Ralph N. Wall, Pocatello, ID (US); and Mark Griswold, Gilbert, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Jul. 19, 2024, as Appl. No. 18/777,737.
Application 18/777,737 is a continuation of application No. 17/662,263, filed on May 6, 2022, granted, now 12,087,760.
Prior Publication US 2024/0387510 A1, Nov. 21, 2024
Int. Cl. H10D 89/60 (2025.01); H10D 84/85 (2025.01)
CPC H10D 89/713 (2025.01) [H10D 84/859 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a region of semiconductor material comprising:
a top side;
a bottom side opposite to the top side;
a semiconductor substrate characterized by a first conductivity type; and
a semiconductor region over the semiconductor substrate and characterized by the first conductivity type and a dopant concentration greater than that of the semiconductor substrate;
a well region in the semiconductor region and characterized by a second conductivity type opposite to the first conductivity type;
a first doped region in the well region and characterized by the first conductivity type;
a second doped region in the well region and characterized by the second conductivity type;
a third doped region in the semiconductor substrate at the bottom side and characterized by the second conductivity type, a first lateral side, and a second lateral side opposite to the first lateral side;
a fourth doped region in the semiconductor substrate at the bottom side and characterized by the first conductivity type, wherein:
the fourth doped region comprises a first portion and a second portion;
the first portion abuts a first lateral side of the third doped region; and
the second portion abuts the second lateral side of the third doped region;
a first conductor coupled to the first doped region and the second doped region at the top side; and
a second conductor coupled to the third doped region and the fourth doped region at the bottom side;
wherein:
the semiconductor device is configured as a dual-sided semiconductor-controlled rectifier (SCR) device.