US 12,284,830 B2
Display panel and display device
Qingjun Lai, Xiamen (CN); Yihua Zhu, Xiamen (CN); Yong Yuan, Xiamen (CN); Ping An, Xiamen (CN); and Zhaokeng Cao, Xiamen (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Oct. 27, 2023, as Appl. No. 18/384,584.
Application 18/384,584 is a continuation of application No. 17/452,969, filed on Oct. 29, 2021, granted, now 11,830,882.
Claims priority of application No. 202011612371.7 (CN), filed on Dec. 30, 2020.
Prior Publication US 2024/0063228 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3225 (2016.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01)
CPC H10D 86/60 (2025.01) [G09G 3/3225 (2013.01); H10D 86/431 (2025.01); H10D 86/471 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); H10D 86/423 (2025.01); H10K 59/1213 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a base substrate;
a first transistor and a second transistor; wherein:
the first transistor and the second transistor are formed on the base substrate; the first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the first active layer includes silicon; the second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; and the second active layer includes an oxide semiconductor;
a length of a channel region of the first transistor is L1; and along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1;
the first transistor further includes a third gate electrode; and along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, wherein D1<D3; and
a length of a channel region of the second transistor is L2; along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the first transistor is included in the pixel circuit, the second transistor is included in one of the pixel circuit and the drive circuit, the first transistor is a drive transistor of the pixel circuit, and (D1/D2)<(L1/L2).