US 12,284,828 B2
Semiconductor device
Atsushi Okamoto, Yokohama (JP); Hirotaka Takeno, Yokohama (JP); and Wenzhen Wang, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on May 31, 2022, as Appl. No. 17/829,341.
Application 17/829,341 is a continuation of application No. PCT/JP2019/047688, filed on Dec. 5, 2019.
Prior Publication US 2022/0293634 A1, Sep. 15, 2022
Int. Cl. H10D 84/90 (2025.01)
CPC H10D 84/907 (2025.01) [H10D 84/975 (2025.01); H10D 84/981 (2025.01); H10D 84/992 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and
a second chip formed on a second surface of the substrate opposite to the first surface of the substrate, the second chip including a second wiring layer formed on the second surface of the substrate opposite to the first surface of the substrate, wherein:
the second wiring layer of the second chip includes;
a first power line to which a first power potential is applied,
a second power line to which a second power potential is applied,
a third power line to which a third power potential is applied,
a first switch connected between the first power line and the second power line, and
a second switch provided on one of the first power line or the third power line, and
the first chip includes a first circuit provided between the first power line and the third power line.