US 12,284,826 B2
Fin end plug structures for advanced integrated circuit structure fabrication
Byron Ho, Hillsboro, OR (US); Chun-Kuo Huang, Portland, OR (US); Erica Thompson, Beaverton, OR (US); Jeanne Luce, Hillsboro, OR (US); Michael L. Hattendorf, Portland, OR (US); Christopher P. Auth, Portland, OR (US); and Ebony L. Mays, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 12, 2024, as Appl. No. 18/412,236.
Application 16/906,680 is a division of application No. 15/859,351, filed on Dec. 30, 2017, granted, now 10,734,379, issued on Aug. 4, 2020.
Application 18/412,236 is a continuation of application No. 17/736,029, filed on May 3, 2022, granted, now 11,961,838.
Application 17/736,029 is a continuation of application No. 17/076,425, filed on Oct. 21, 2020, granted, now 11,380,683, issued on Jul. 5, 2022.
Application 17/076,425 is a continuation of application No. 16/906,680, filed on Jun. 19, 2020, granted, now 10,861,850, issued on Dec. 8, 2020.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2024/0153947 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/834 (2025.01) [H01L 21/76232 (2013.01); H10D 30/024 (2025.01); H10D 30/0245 (2025.01); H10D 30/6211 (2025.01); H10D 30/792 (2025.01); H10D 30/795 (2025.01); H10D 30/797 (2025.01); H10D 62/116 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a fin along a direction;
a first isolation structure at and in contact with a first end of the fin, wherein the first isolation structure has a top surface above the top of the fin;
a gate structure comprising a gate electrode over a channel region of the fin, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure at and in contact with a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the fin, and wherein the first isolation structure and the second isolation structure each comprise a first dielectric material having a lower portion laterally surrounding a second dielectric material, the second dielectric material laterally surrounding at least a portion of a third dielectric material, and a fourth dielectric material above the second dielectric material and the third dielectric material, the four dielectric material laterally surrounded by an upper portion of the first dielectric material.