| CPC H10D 64/017 (2025.01) [H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 12 Claims |
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1. A method for manufacturing a metal gate of a semiconductor device, comprising the following steps:
step 1: providing a semiconductor substrate, forming a polysilicon dummy gate on the semiconductor substrate, wherein a spacer region is configured to be around the polysilicon dummy gate, forming a first gate dielectric layer between the polysilicon dummy gate and a surface of the semiconductor substrate, forming a first hard mask layer on a top surface of the polysilicon dummy gate, and forming a second hard mask layer on a top surface of the first hard mask layer;
step 2: forming a low dielectric constant sidewall layer on side surfaces of the second hard mask layer, the first hard mask layer, and the polysilicon dummy gate, wherein the step 2 comprises the following sub-steps:
step 21: forming a first protective layer, wherein the first protective layer is disposed on a top surface and the side surfaces of the second hard mask layer, on the side surfaces of the first hard mask layer, and on the side surfaces of the polysilicon dummy gate, wherein the first protective layer is also disposed on a portion of the surface of the semiconductor substrate not under the polysilicon dummy gate;
step 22: forming a second low dielectric constant layer on an outer surface of the first protective layer, wherein the first protective layer has a higher thermal stability and a higher etching resistance than a thermal stability and an etching resistance of the second low dielectric constant layer;
step 23: forming a third protective layer on an outer surface of the second low dielectric constant layer, wherein a thermal stability and an etching resistance of the third protective layer are higher than the thermal stability and etching resistance of the second low dielectric constant layer,
wherein the first protective layer, the second low dielectric constant layer, and the third protective layer combine to constitute the low dielectric constant sidewall layer in the spacer region at sides of the polysilicon dummy gate;
step 24: removing by etching the low dielectric constant sidewall layer from the top surface of the second hard mask layer, and from a part of the portion of the surface of the semiconductor substrate not under the low dielectric constant sidewall layer, in the spacer region;
step 3: forming a contact etch stop layer on the top surface of the second hard mask layer, on sides of the remaining low dielectric constant sidewall layer, and on the part of the portion of the surface of the semiconductor substrate not under the polysilicon dummy gate;
forming a zeroth interlayer film on a top surface of the contact etch stop layer in the spacer region, and removing, by polishing, the zeroth interlayer film and the contact etch stop layer on the first and second hard mask layers, and the contact etch stop layer on a part of the low dielectric constant sidewall layer to be flush with the top surface of the polysilicon dummy gate, wherein a top surface of the zeroth interlayer film in the spacer region is flush with the top surface of the polysilicon dummy gate; and
step 4: performing gate replacement, wherein the step 4 comprises the following sub-steps:
step 41: removing the polysilicon dummy gate, and forming a gate trench from where the polysilicon dummy gate is removed; and
step 42: forming the metal gate in the gate trench.
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