US 12,284,821 B2
Semiconductor devices
Junghwan Chun, Anyang-si (KR); Hongsik Shin, Seoul (KR); Koungmin Ryu, Hwaseong-si (KR); Bongkwan Baek, Seoul (KR); and Jongmin Baek, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 27, 2022, as Appl. No. 17/849,797.
Claims priority of application No. 10-2021-0118399 (KR), filed on Sep. 6, 2021.
Prior Publication US 2023/0072817 A1, Mar. 9, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6729 (2025.01) [H01L 21/02603 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an active region extending on a substrate in a first direction;
a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure;
a source/drain region on the active region adjacent the gate structure; and
a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure,
wherein the capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and
the second contact plug penetrates through the capping layer, is connected to the gate electrode, and includes a convex sidewall curved toward the upper capping layer.