| CPC H10D 30/605 (2025.01) [H10D 64/118 (2025.01); H10D 64/664 (2025.01)] | 20 Claims |
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1. A transistor structure comprising:
a substrate having a top planar surface;
a monolithic epitaxial source region formed entirely over the top planar surface;
a monolithic epitaxial drain region formed entirely over the top planar surface and separated from the source region by a gap, wherein inner sidewalls of the source and drain regions define the gap;
an isolation layer having a first portion formed on top surfaces and a second portion formed on inner sidewalls on the source and drain regions;
a gate dielectric formed in the gap and contacting the substrate; and
a gate electrode comprising:
a first region having a first width formed in the gap between the second portion of the isolation structure and contacting the gate dielectric; and
a second region having a second width greater than the first width, wherein the second region overlaps the first portion of the isolation layer.
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