US 12,284,817 B2
Trench-gated heterostructure and double-heterostructure active devices
Jun Zeng, Torrance, CA (US); and Mohamed N. Darwish, Campbell, CA (US)
Assigned to MaxPower Semiconductor Inc., San Jose, CA (US)
Filed by MaxPower Semiconductor Inc., San Jose, CA (US)
Filed on Jun. 12, 2018, as Appl. No. 16/006,693.
Application 16/006,693 is a continuation in part of application No. 15/620,547, filed on Jun. 12, 2017, abandoned.
Claims priority of provisional application 62/518,486, filed on Jun. 12, 2017.
Claims priority of provisional application 62/348,783, filed on Jun. 10, 2016.
Prior Publication US 2018/0366569 A1, Dec. 20, 2018
Int. Cl. H01L 21/324 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2025.01); H01L 21/285 (2006.01); H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/473 (2025.01) [H01L 21/02164 (2013.01); H01L 21/049 (2013.01); H01L 21/28185 (2013.01); H01L 21/324 (2013.01); H10D 12/031 (2025.01); H10D 12/038 (2025.01); H10D 12/461 (2025.01); H10D 12/481 (2025.01); H10D 30/015 (2025.01); H10D 30/0291 (2025.01); H10D 30/0295 (2025.01); H10D 30/0297 (2025.01); H10D 30/4732 (2025.01); H10D 30/477 (2025.01); H10D 30/668 (2025.01); H10D 62/107 (2025.01); H10D 62/136 (2025.01); H10D 62/137 (2025.01); H10D 62/154 (2025.01); H10D 62/157 (2025.01); H10D 62/158 (2025.01); H10D 62/393 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01); H10D 64/112 (2025.01); H10D 64/117 (2025.01); H10D 64/513 (2025.01); H01L 21/02274 (2013.01); H01L 21/047 (2013.01); H01L 21/26513 (2013.01); H01L 21/28035 (2013.01); H01L 21/28568 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A double-heterostructure semiconductor device structure, comprising:
at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material;
wherein the first and third semiconductor materials are each different from the second semiconductor material;
a first-conductivity-type source region abutting a second-conductivity-type body region, formed in the first semiconductor material;
a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material;
a gate which is positioned in a first trench within at least said first semiconductor material and said second semiconductor material, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench;
recessed field plates, positioned in proximity to and capacitively coupled to at least said first semiconductor material and said second semiconductor material; said recessed field plates being positioned in respective second trenches;
wherein the first and second trenches both extend through the first semiconductor material down into the second semiconductor material; and
a first additional diffusion component of a second conductivity type lying at least partially beneath said respective second trenches,
wherein the first semiconductor material is silicon, the second semiconductor material is silicon carbide, and the third semiconductor material is silicon.
 
7. A double-heterostructure semiconductor device structure, comprising:
at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material;
wherein the first and third semiconductor materials are each different from the second semiconductor material;
a first-conductivity-type source region abutting a second-conductivity-type body region, formed in the first semiconductor material;
a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material;
a gate which is positioned in a first trench within at least said first semiconductor material and said second semiconductor material, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench;
recessed field plates, positioned in proximity to and capacitively coupled to at least said first semiconductor material and said second semiconductor material; said recessed field plates being positioned in respective second trenches;
wherein the first and second trenches both extend through the first semiconductor material down into the second semiconductor material; and
a first additional diffusion component of a second conductivity type lying at least partially beneath said respective second trenches,
wherein the first semiconductor material is a III-N semiconductor material, the second semiconductor material is a IV-IV semiconductor alloy, and the third semiconductor material is silicon.
 
8. A double-heterostructure semiconductor device structure, comprising:
at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material;
wherein the first and third semiconductor materials are each different from the second semiconductor material;
a first-conductivity-type source region abutting a second-conductivity-type body region, formed in the first semiconductor material;
a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material;
a gate which is positioned in a first trench within at least said first semiconductor material and said second semiconductor material, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench;
recessed field plates, positioned in proximity to and capacitively coupled to at least said first semiconductor material and said second semiconductor material; said recessed field plates being positioned in respective second trenches;
wherein the first and second trenches both extend through the first semiconductor material down into the second semiconductor material; and
a first additional diffusion component of a second conductivity type lying at least partially beneath said respective second trenches,
wherein the first semiconductor material is silicon, the second semiconductor material is a III-N semiconductor material, and the third semiconductor material is a Group IV semiconductor material.
 
9. A double-heterostructure semiconductor device structure, comprising:
at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material;
wherein the first and third semiconductor materials are each different from the second semiconductor material;
a first-conductivity-type source or emitter region surrounded by a second-conductivity-type body region, formed in the first semiconductor material;
a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material;
a gate which is positioned in a first trench within at least said first semiconductor material, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench,
wherein the first semiconductor material is silicon, the second semiconductor material is silicon carbide, and the third semiconductor material is silicon.
 
14. A double-heterostructure semiconductor device structure, comprising:
at least one layer of a first semiconductor material epitaxially overlying at least one layer of a second semiconductor material which epitaxially overlies at least one layer of a third semiconductor material;
wherein the first and third semiconductor materials are each different from the second semiconductor material;
a first-conductivity-type source or emitter region surrounded by a second-conductivity-type body region, formed in the first semiconductor material;
a first-conductivity-type drift region abutting the body region, and formed in the second semiconductor material;
a gate which is positioned in a first trench within at least said first semiconductor material, and is capacitively coupled to control vertical conduction from the source region through portions of the body region near said trench,
wherein the first semiconductor material is a III-N semiconductor material, the second semiconductor material is a IV-IV semiconductor alloy, and the third semiconductor material is silicon.