US 12,284,816 B2
Semiconductor structures having deep trench capacitor and methods for manufacturing the same
Szu-Yu Hou, New Taipei (TW); and Li-Han Lin, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Jul. 3, 2024, as Appl. No. 18/763,075.
Application 18/763,075 is a division of application No. 18/219,247, filed on Jul. 7, 2023, granted, now 12,148,791.
Application 18/219,247 is a division of application No. 17/888,749, filed on Aug. 16, 2022, granted, now 12,183,778.
Prior Publication US 2024/0355871 A1, Oct. 24, 2024
Int. Cl. H10D 1/68 (2025.01); H10B 12/00 (2023.01); H10D 1/00 (2025.01)
CPC H10D 1/696 (2025.01) [H10B 12/01 (2023.02); H10B 12/033 (2023.02); H10B 12/0387 (2023.02); H10B 12/31 (2023.02); H10D 1/042 (2025.01); H10D 1/043 (2025.01); H10D 1/716 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a plurality of layers on the substrate, wherein the plurality of layers include:
a first nitride layer on the substrate;
a first silicon-containing layer on the first nitride layer;
an intermediate layer on the first silicon-containing layer;
a second silicon-containing layer on the intermediate layer; and
a second nitride layer on the second silicon-containing layer;
performing a first removal operation on the plurality of layers to form a trench, the trench penetrating the first nitride layer, the first silicon-containing layer, the intermediate layer, the second silicon-containing layer, and the second nitride layer, wherein the trench includes a first portion surrounded by the first silicon-containing layer and a second portion surrounded by the second silicon-containing layer; and
performing a second removal operation on the plurality of layers to expand the first portion of the trench;
wherein the substrate includes a conductive region exposed from the plurality of layers;
wherein the first silicon-containing layer includes a first region adjacent to the first nitride layer and a second region on the first region;
wherein the first region of the first silicon-containing layer has a first doping concentration, and the second region of the first silicon-containing layer has a second doping concentration greater than the first doping concentration; wherein the first region of the first silicon-containing layer has a thickness greater than that of the second region of the first silicon-containing layer.