US 12,284,815 B2
Multilayer-type on-chip inductor structure
Sheng-Yuan Lee, New Taipei (TW)
Assigned to VIA LABS, INC., New Taipei (TW)
Filed by VIA LABS, INC., New Taipei (TW)
Filed on Mar. 9, 2022, as Appl. No. 17/690,580.
Claims priority of application No. 110149356 (TW), filed on Dec. 29, 2021.
Prior Publication US 2023/0207612 A1, Jun. 29, 2023
Int. Cl. H01L 23/522 (2006.01); H01F 17/00 (2006.01); H10D 1/20 (2025.01)
CPC H10D 1/20 (2025.01) [H01F 17/0013 (2013.01); H01L 23/5227 (2013.01); H01F 2017/0086 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A multilayer-type on-chip inductor structure, comprising:
a first winding portion disposed in an inter-metal dielectric (IMD) layer and including a first semi-circular stacking layer and a second semi-circular stacking layer arranged from inside to outside and in concentricity, and a first input/output conductive portion disposed on the outside of the second semi-circular stacking layer;
a second winding portion, disposed in the IMD layer and including a third semi-circular stacking layer and a fourth semi-circular stacking layer arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis, and a second input/output conductive portion disposed on the outside of the fourth semi-circular stacking layer;
a conductive branch layer disposed in an insulating redistribution layer over the IMD layer and electrically coupled to the first semi-circular stacking layer and the third semi-circular stacking layer,
wherein the first semi-circular stacking layer, the second semi-circular stacking layer, the first input/output conductive portion, the third semi-circular stacking layer, the fourth semi-circular stacking layer, and the second input/output conductive portion each comprises:
an uppermost trace layer; and
a next uppermost trace layer vertically stacked under the uppermost trace layer and electrically coupled thereto.