US 12,284,814 B2
Semiconductor structure and manufacturing method of the same
Harry-Hak-Lay Chuang, Paya Lebar Crescent (SG); Sheng-Huang Huang, Hsinchu (TW); Keng-Ming Kuo, Yunlin County (TW); and Hung Cho Wang, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 21, 2023, as Appl. No. 18/338,509.
Application 17/244,768 is a division of application No. 16/884,883, filed on May 27, 2020, granted, now 10,998,377, issued on May 4, 2021.
Application 16/884,883 is a division of application No. 15/962,434, filed on Apr. 25, 2018, granted, now 10,727,272, issued on Jul. 28, 2020.
Application 18/338,509 is a continuation of application No. 17/244,768, filed on Apr. 29, 2021, granted, now 11,723,219.
Claims priority of provisional application 62/590,465, filed on Nov. 24, 2017.
Prior Publication US 2023/0345739 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a memory region;
a logic region adjacent to the memory region;
a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region;
a carbon-based layer over the memory region; and
a bottom electrode via under the first MTJ cell, wherein an uppermost surface of the bottom electrode via is above an uppermost surface of the carbon-based layer;
wherein a bottom portion of the bottom electrode via is free from being surrounded by the carbon-based layer.