US 12,284,813 B2
Nonvolatile memory device including dual memory layers
Zhiqiang Wei, Pleasanton, CA (US); Zihui Wang, Mountain View, CA (US); Ebrahim Abedifard, San Jose, CA (US); and Yiming Huai, Pleasanton, CA (US)
Assigned to Avalanche Technology, Inc., Fremont, CA (US)
Filed by Avalanche Technology, Inc., Fremont, CA (US)
Filed on Feb. 6, 2023, as Appl. No. 18/106,159.
Prior Publication US 2024/0268125 A1, Aug. 8, 2024
Int. Cl. H10B 61/00 (2023.01); H01L 23/528 (2006.01); H10N 50/10 (2023.01)
CPC H10B 61/22 (2023.02) [H01L 23/5283 (2013.01); H10N 50/10 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a plurality of first conductive lines extending along a first direction;
first and second plurality of second conductive lines extending along a second direction;
an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends of each active region along the third direction; and
an array of first memory elements and an array of second memory elements formed at different levels with respect to the array of active regions, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively,
wherein the first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.