| CPC H10B 61/00 (2023.02) [G11C 11/161 (2013.01); H10B 61/10 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 9 Claims |
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1. A semiconductor structure, comprising:
a substrate having a memory device region and a logic device region;
a first dielectric layer on the substrate;
a plurality of memory stack structures on the first dielectric layer on the memory device region;
an insulating layer conformally covering the memory stack structures and the first dielectric layer, wherein a thickness of the insulating layer on sidewalls of the memory stack structures is larger than a thickness of the insulating layer on the first dielectric layer;
a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures;
a first interconnecting structure formed in the second dielectric layer on the logic device region, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures;
a third dielectric layer on the second dielectric layer; and
a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
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