US 12,284,810 B2
Memory device and manufacturing method thereof
Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); Feng-Cheng Yang, Hsinchu County (TW); Bo-Feng Young, Taipei (TW); Nuo Xu, San Jose, CA (US); Sai-Hooi Yeong, Hsinchu County (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/354,667.
Application 18/354,667 is a division of application No. 17/327,752, filed on May 23, 2021, granted, now 11,910,615.
Claims priority of provisional application 63/137,754, filed on Jan. 15, 2021.
Prior Publication US 2023/0363172 A1, Nov. 9, 2023
Int. Cl. H10B 51/20 (2023.01); H10B 51/10 (2023.01)
CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a word line extending in a first direction;
liner layers disposed on a sidewall of the word line;
a memory layer, disposed on the sidewall of the word line between the liner layers and extending along sidewalls of the liner layers in the first direction, wherein the liner layers are spaced apart by the memory layer and the liner layers are sandwiched between the memory layer and the word line;
a channel material layer disposed on a sidewall of the memory layer;
a dielectric layer disposed on a sidewall of the channel material layer; and
a source line and a bit line, disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer, wherein the source line and the bit line extend in a second direction perpendicular to the first direction,
wherein a material of the liner layers has a dielectric constant lower than that of a material of the memory layer.