US 12,284,809 B2
Semiconductor memory device and method of manufacturing the same
Jae Taek Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 5, 2022, as Appl. No. 17/737,479.
Claims priority of application No. 10-2021-0182113 (KR), filed on Dec. 17, 2021.
Prior Publication US 2023/0200068 A1, Jun. 22, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction;
a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body;
a memory layer enclosing a sidewall of the channel structure; and
a source layer formed on the gate stacked body,
wherein the channel structure comprises:
a core insulating layer formed in a central region of the channel structure and extending in a vertical direction; and
a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.