| CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02)] | 15 Claims |

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1. A semiconductor memory device, comprising:
a source structure; and
a gate stacked structure disposed over the source structure, the gate stacked structure having a cell array region and a contact region with a stepped shape,
wherein a roughness of a first sidewall of the cell array region of the gate stacked structure is greater than that of a second sidewall of the contact region of the gate stacked structure.
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