US 12,284,807 B2
Three-dimensional memory device with separated contact regions
Hiroyuki Ogawa, Nagoya (JP); Hardwell Chibvongodze, Hiratsuka (JP); Zhixin Cui, Nagoya (JP); and Rajdeep Gautam, Nagoya (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Aug. 9, 2021, as Appl. No. 17/397,777.
Prior Publication US 2023/0038557 A1, Feb. 9, 2023
Int. Cl. H10B 43/27 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, wherein the alternating stack laterally extends through a series of regions that comprises, in a spatial order along a first horizontal direction, a first contact region, a first memory array region, an auxiliary contact region, a second memory array region, and a second contact region;
forming arrays of memory openings located in the first memory array region and the second memory array region; and
forming arrays of memory opening fill structures within the arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements,
wherein the alternating stack comprises a lower layer stack including a first subset of the insulating layers and a first subset of the electrically conductive layers located underneath a horizontal plane, a first upper layer stack including a second subset of the insulating layers and a second subset of the electrically conductive layers located above the horizontal plane, and a second upper layer stack including a third subset of the insulating layers and a third subset of the electrically conductive layers located above the horizontal plane and laterally spaced apart from the first upper layer stack;
wherein the lower layer stack laterally extends through a series of regions that comprises, in a spatial order along a first horizontal direction, a first contact region, a first memory array region, an auxiliary contact region, a second memory array region, and a second contact region; and
wherein the first upper layer stack laterally extends through the first memory array region and a first portion of the auxiliary contact region, and the second upper layer stack laterally extends through a second portion of the auxiliary contact region and the second memory array region.