US 12,284,806 B2
Semiconductor device and method of manufacturing the same
Meng-Han Lin, Hsinchu (TW); Chih-Ren Hsieh, Changhua (TW); and Ching-Wen Chan, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinch (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 21, 2023, as Appl. No. 18/515,961.
Application 16/585,809 is a division of application No. 15/698,469, filed on Sep. 7, 2017, granted, now 10,770,469, issued on Sep. 8, 2020.
Application 18/515,961 is a continuation of application No. 17/567,613, filed on Jan. 3, 2022, granted, now 11,864,381.
Application 17/567,613 is a continuation of application No. 16/585,809, filed on Sep. 27, 2019, granted, now 11,217,597, issued on Jan. 4, 2022.
Claims priority of provisional application 62/439,739, filed on Dec. 28, 2016.
Prior Publication US 2024/0090216 A1, Mar. 14, 2024
Int. Cl. H10B 41/50 (2023.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 41/43 (2023.01)
CPC H10B 41/50 (2023.02) [H10B 41/40 (2023.02); H10B 41/43 (2023.02); H10B 41/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a non-volatile memory disposed over a substrate in a memory cell area;
a logic circuit disposed over the substrate in a peripheral area;
a protrusion of the substrate disposed between the memory cell area and the peripheral area,
wherein the protrusion surrounds the memory cell area in plan view and the protrusion extends from the substrate along a first direction;
a first isolation insulating layer disposed in the substrate between the memory cell area and the protrusion;
a second isolation insulating layer disposed in the substrate between the protrusion and the peripheral area;
a first dielectric layer disposed over the first isolation insulating layer and the protrusion;
a first poly silicon layer disposed over the first dielectric layer;
a second dielectric layer disposed over the protrusion and the second isolation insulating layer,
wherein the second dielectric layer is spaced apart from the first dielectric layer; and
a second poly silicon layer disposed over the second dielectric layer,
wherein the second poly silicon layer is spaced apart from the first poly silicon layer,
wherein a height of an uppermost surface of the protrusion along the first direction is greater than a height of an uppermost surface of the second isolation insulating layer along the first direction, and
wherein the height of the uppermost surface of the second isolation insulating layer along the first direction is greater than a height of the first isolation insulating layer along the first direction.