| CPC H10B 41/35 (2023.02) [H01L 21/76877 (2013.01); H01L 21/823412 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/24 (2013.01); H01L 29/78621 (2013.01); H01L 29/78681 (2013.01); H01L 29/78696 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 18 Claims | 

| 
               8. A memory device, comprising: 
              blocks horizontally extending in parallel a first direction and each comprising tiers individually including conductive material and insulative material vertically neighboring the conductive material, the blocks respectively comprising: 
                an array region; and 
                  a staircase region neighboring the array region in the first direction and comprising a staircase structure having steps comprising edges of at least some of the tiers; 
                microelectronic devices vertically overlying the blocks and individually horizontally extending in a second direction perpendicular to the first direction over two of the blocks, the microelectronic devices respectively comprising: 
              dielectric fin structures horizontally extending in parallel in the second direction; 
                  a two-dimensional (2D) material substantially conformally extending on and between the dielectric fin structures, the 2D material comprising a first channel region and a second channel region; 
                  dielectric material on the 2D material; and 
                  gate electrodes on the dielectric material and extending in parallel the first direction and comprising a first gate electrode and a second gate electrode, 
                  the first channel region of the 2D material horizontally overlapping, in the second direction, each of a first block of the two of the blocks and the first gate electrode, and 
                  the second channel region of the 2D material horizontally overlapping, in the second direction, each of a second block of the two of the blocks and the second gate electrode; and 
                conductive contacts coupling respective ones of the microelectronic devices with the conductive material of respective ones of the tiers of the two of the blocks horizontally overlapping the respective ones of the microelectronic devices in the second direction. 
             |