US 12,284,802 B2
Semiconductor structure and method for manufacturing semiconductor structure
Zhaopei Cui, Hefei (CN); and Bingyu Zhu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 14, 2022, as Appl. No. 17/650,985.
Application 17/650,985 is a continuation of application No. PCT/CN2021/111835, filed on Aug. 10, 2021.
Claims priority of application No. 202110350105.X (CN), filed on Mar. 31, 2021.
Prior Publication US 2022/0320109 A1, Oct. 6, 2022
Int. Cl. H01L 27/108 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/30 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a bit line array on an upper surface of the substrate, wherein the bit line array comprises a plurality of bit lines arranged in parallel at intervals, the bit lines are connected through at least one support pattern, the at least one support pattern crosses through the bit line array along an arrangement direction of the bit lines, each of the at least one support pattern extends along a first direction, and each of the bit lines extends along a second direction;
forming a bit line side wall on side walls of each of the bit lines, wherein the bit line side wall comprises a first side wall dielectric layer, a sacrificial layer and a second side wall dielectric layer which are stacked in sequence, and the bit line side wall and the bit lines constitute a plurality of bit line structures;
forming a filling dielectric layer between two adjacent bit line structures of the bit line structures, an upper surface of the filling dielectric layer being flush with upper surfaces of the bit line structures;
forming at least one groove in the at least one support pattern, the at least one groove exposing the sacrificial layer, wherein the sacrificial layer comprises at least one recess at an upper edge of the sacrificial layer; and
based on the at least one groove, removing the sacrificial layer by wet etching to form an air gap between the first side wall dielectric layer and the second side wall dielectric layer, wherein the air gap comprises the at least one recess at an upper edge of the air gap.