US 12,284,359 B2
Early notification for a low latency video decoder
Tomoyuki Naito, San Diego, CA (US); and Yasutomo Matsuba, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 5, 2023, as Appl. No. 18/150,649.
Prior Publication US 2024/0236333 A1, Jul. 11, 2024
Int. Cl. H04N 19/146 (2014.01); H04N 19/117 (2014.01); H04N 19/119 (2014.01); H04N 19/136 (2014.01); H04N 19/182 (2014.01)
CPC H04N 19/146 (2014.11) [H04N 19/117 (2014.11); H04N 19/119 (2014.11); H04N 19/136 (2014.11); H04N 19/182 (2014.11)] 26 Claims
OG exemplary drawing
 
1. An apparatus for processing video data, comprising:
a memory; and
a processor coupled to a memory, the processor being configured to:
obtain an indication of a target latency;
determine a number of rows of pixels for a first portion of an image based on the target latency;
obtain first encoded data for the first portion of the image;
decode the first encoded data to generate first pixel data for the number of rows of pixels of the first portion of the image;
output the first pixel data for the first portion of the image to the memory; and
output an indication that the first portion of the image is available.