US 12,284,353 B2
Arithmetic coding for information related to sample adaptive offset processing
Toru Matsunobu, Osaka (JP); Takahiro Nishi, Nara (JP); Youji Shibahara, Osaka (JP); Hisao Sasai, Osaka (JP); Kyoko Tanikawa, Osaka (JP); Toshiyasu Sugio, Osaka (JP); and Kengo Terada, Osaka (JP)
Assigned to SUN PATENT TRUST, New York, NY (US)
Filed by Sun Patent Trust, New York, NY (US)
Filed on Nov. 8, 2023, as Appl. No. 18/387,917.
Application 18/387,917 is a continuation of application No. 17/824,109, filed on May 25, 2022, granted, now 11,849,116.
Application 17/824,109 is a continuation of application No. 17/022,672, filed on Sep. 16, 2020, granted, now 11,375,195.
Application 17/022,672 is a continuation of application No. 16/239,927, filed on Jan. 4, 2019, granted, now 10,812,800, issued on Oct. 20, 2020.
Application 16/239,927 is a continuation of application No. 15/014,374, filed on Feb. 3, 2016, granted, now 10,212,425, issued on Feb. 19, 2019.
Application 15/014,374 is a continuation of application No. 13/908,278, filed on Jun. 3, 2013, granted, now 9,305,367, issued on Apr. 5, 2016.
Claims priority of provisional application 61/657,183, filed on Jun. 8, 2012.
Prior Publication US 2024/0073422 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/94 (2006.01); A61F 13/00 (2024.01); A61F 13/05 (2024.01); A61M 1/00 (2006.01); G06T 9/00 (2006.01); H04N 19/117 (2014.01); H04N 19/13 (2014.01); H04N 19/136 (2014.01); H04N 19/157 (2014.01); H04N 19/169 (2014.01); H04N 19/189 (2014.01); H04N 19/196 (2014.01); H04N 19/46 (2014.01); H04N 19/61 (2014.01); H04N 19/70 (2014.01); H04N 19/80 (2014.01); H04N 19/82 (2014.01); H04N 19/86 (2014.01)
CPC H04N 19/13 (2014.11) [A61F 13/05 (2024.01); A61M 1/732 (2021.05); A61M 1/962 (2021.05); G06T 9/00 (2013.01); H04N 19/117 (2014.11); H04N 19/136 (2014.11); H04N 19/157 (2014.11); H04N 19/1887 (2014.11); H04N 19/189 (2014.11); H04N 19/196 (2014.11); H04N 19/46 (2014.11); H04N 19/61 (2014.11); H04N 19/70 (2014.11); H04N 19/80 (2014.11); H04N 19/82 (2014.11); H04N 19/86 (2014.11); A61F 2013/00174 (2013.01); A61F 2013/0057 (2013.01); A61F 2013/0091 (2013.01); A61F 2013/00944 (2013.01); A61F 2013/00957 (2013.01); A61M 2205/15 (2013.01); A61M 2205/3592 (2013.01); A61M 2205/8206 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A coding circuit comprising:
context arithmetic coding circuitry that performs context arithmetic coding to code (i) first information indicating whether or not to use, in sample adaptive offset (SAO) processing for a first region of an image, information on SAO processing for a region other than the first region and (ii) second information indicating whether or not to perform the SAO processing for the first region, the context arithmetic coding being arithmetic coding using a variable probability, the SAO processing being offset processing on a pixel value; and
bypass arithmetic coding circuitry that performs bypass arithmetic coding to code other information, the other information being information on the SAO processing for the first region and different from the first information and the second information, the other information being coded after the first information and the second information are coded, the bypass arithmetic coding being arithmetic coding using a fixed probability,
wherein the other information includes (i) third information indicating whether the SAO processing for the first region is edge offset processing or band offset processing and (ii) fourth information indicating an absolute value of an offset value, the edge offset processing being performed according to an edge, the band offset processing being performed according to a pixel value, and
wherein when the SAO processing for the first region is the band offset processing, the other information includes (i) fifth information indicating whether the offset value is positive or negative and (ii) sixth information indicating a scope of application of the offset value.