US 12,283,972 B2
Method and system for error correction in memory devices using irregular error correction code components
Ofir Kanter, Tel Aviv (IL); Avi Steiner, Tel Aviv (IL); Amir Nassie, Tel Aviv (IL); and Hanan Weingarten, Tel Aviv (IL)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 26, 2023, as Appl. No. 18/341,041.
Application 18/341,041 is a division of application No. 17/401,215, filed on Aug. 12, 2021, granted, now 11,689,219.
Prior Publication US 2023/0336190 A1, Oct. 19, 2023
Int. Cl. H03M 13/11 (2006.01); H03M 13/29 (2006.01)
CPC H03M 13/118 (2013.01) [H03M 13/2909 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An error correction system, comprising:
a first syndrome calculation cell operable to receive a first code component input and to generate a first error correction syndrome output corresponding to the first code component input; and
a second syndrome calculation cell operable to receive the first code component input and to generate a second error correction syndrome output corresponding to the first code component input,
wherein the first syndrome calculation cell and the second syndrome calculation cell are both configured to generate error correction syndrome outputs corresponding to code component inputs having both a first number of bits and a second different number of bits.