US 12,283,969 B2
Time-interleaved analog to digital converter based on control of counter
Shih-Hsiung Huang, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Apr. 20, 2023, as Appl. No. 18/137,079.
Claims priority of application No. 111137117 (TW), filed on Sep. 29, 2022.
Prior Publication US 2024/0113726 A1, Apr. 4, 2024
Int. Cl. H03M 1/12 (2006.01); H03M 1/50 (2006.01)
CPC H03M 1/50 (2013.01) [H03M 1/1245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A time-interleaved analog to digital converter, comprising:
a plurality of capacitor array circuits configured to sequentially sample an input signal and generate a plurality of first residue signals according to a plurality of first quantization signals, wherein the plurality of first quantization signals are generated based on a coarse analog to digital conversion performed based on the input signal;
a plurality of first transfer circuits configured to sequentially transfer the plurality of first residue signals from the plurality of capacitor array circuits according to a plurality of first control signals;
a fine converter circuitry configured to perform a noise shaping signal conversion on a first signal in the plurality of first residue signals and a second signal in a plurality of second residue signals according to a conversion control signal, in order to generate a second quantization signal;
a control circuitry configured to count according to the second quantization signal to generate a count signal and the conversion control signal, and output the count signal to be a switching signal according to the plurality of first control signals;
a plurality of second transfer circuits configured to sequentially transfer the plurality of second residue signals from the plurality of capacitor array circuits to the fine converter circuitry according to a plurality of second control signals, wherein the plurality of capacitor array circuit are further configured to generate the plurality of second residue signals in response to the noise shaping signal conversion and adjust the plurality of second residue signals according to the switching signal; and
an encoder circuit configured to generate a digital output according to the second quantization signal and a corresponding one of the plurality of first quantization signals.