US 12,283,967 B2
Analog to digital converter with current steering stage
Martin Kinyua, Cedar Park, TX (US); and Eric Soenen, Austin, TX (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 10, 2023, as Appl. No. 18/349,636.
Application 18/349,636 is a continuation of application No. 17/717,519, filed on Apr. 11, 2022, granted, now 11,700,009.
Application 17/717,519 is a continuation of application No. 17/120,438, filed on Dec. 14, 2020, granted, now 11,303,292, issued on Apr. 12, 2022.
Application 17/120,438 is a continuation of application No. 16/359,495, filed on Mar. 20, 2019, granted, now 10,868,557, issued on Dec. 15, 2020.
Claims priority of provisional application 62/650,536, filed on Mar. 30, 2018.
Prior Publication US 2024/0048148 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/38 (2006.01); H03M 1/06 (2006.01); H03M 1/14 (2006.01); H03M 1/16 (2006.01)
CPC H03M 1/145 (2013.01) [H03M 1/0612 (2013.01); H03M 1/164 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC), comprising:
an input terminal configured to receive an analog input voltage;
a current mode digital-to-analog converter (DAC) stage including
a transconductance amplifier (Gm) connected to the input terminal, the transconductance amplifier having a first plurality of transconductance amplifier cells, the transconductance amplifier configured to sample the analog input voltage in response to a first phase clock signal and convert the analog input voltage to a first current signal,
a current mode DAC having a second plurality of current mode DAC unit cells and configured to convert a first digital value corresponding to the analog input voltage to a second current signal,
the current mode DAC stage configured to determine a residue current signal representing a difference between the first current signal and the second current signal, and convert the residue current signal to an analog residual voltage signal;
a residue amplifier configured to convert the residue current signal to analog residue voltage signal, the residue amplifier including first and second stages, the first stage having a wideband self-biased amplifier and the second stage including a common mode feedback circuit;
an alignment and digital error correction stage configured to combine the first digital value and a second digital value representing the analog residue voltage signal into a digital output voltage; and
an output terminal coupled to the alignment and error correction stage configured to output the digital output voltage.