US 12,283,965 B1
Charge pump for fractional-n frequency synthesizer
Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Jan. 3, 2024, as Appl. No. 18/402,838.
Int. Cl. H03L 7/197 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01)
CPC H03L 7/1974 (2013.01) [H03L 7/0891 (2013.01); H03L 7/093 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A divisor ratio charge pump comprising:
a DAC (digital-to-analog converter) configured to draw a first current and a second current from a first node and a second node, respectively, in accordance with a first logical signal, a second logical, and a B-bit control word, wherein B is an integer greater than one;
a CGA (common-gate amplifier) configured to provide a path for charge transfer between the second node and a third node in accordance with a third logical signal;
an integrating capacitor connected to the second node and configured to be either discharged by the DAC or charged by the CGA in accordance with a fourth logical signal; and
a low-impedance active load connected to the first node, wherein:
the first logical signal comprises a first pulse starting at a second time instant that trails a first time instant but leads a third time instant and ending at a fourth time instant that trails the third time instant;
the second logical signal comprises a second pulse starting at the third time instant and ending at the fourth time instant;
the fourth logical signal comprises a fourth pulse starting at the first time instant and ending no earlier than the fourth time instant;
the third logical signal is an inversion of the fourth logical signal; and
a value of the B-bit control word remains fixed during a time window of the fourth pulse.