US 12,283,961 B2
Automatic clock rate synchronization for 1-wire radio frequency front-end interface
Lalan Jee Mishra, Escondido, CA (US); Umesh Srikantiah, San Diego, CA (US); and Richard Dominic Wietfeldt, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 14, 2023, as Appl. No. 18/449,554.
Prior Publication US 2025/0062758 A1, Feb. 20, 2025
Int. Cl. H03K 5/24 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01)
CPC H03K 5/249 (2013.01) [H03K 3/037 (2013.01); H03K 3/356095 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A clock generation circuit, comprising:
a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus;
a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal;
a comparator configured to:
drive a decision signal to a first signaling state when the output of the counter matches the latched output; and
drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and
a flipflop having an output that changes signaling state in response to an edge in the decision signal,
wherein the counter is reset when the decision signal is driven to the first signaling state.