US 12,283,957 B2
Interface device and signal transceiving method thereof
Bi-Yang Li, Hsinchu (TW); Igor Elkanovich, Hsinchu (TW); Hung-Yi Chang, Hsinchu (TW); and Shih-Cheng Kao, Hsinchu (TW)
Assigned to Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Global Unichip Corporation, Hsinchu (TW); and Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 31, 2022, as Appl. No. 17/899,623.
Prior Publication US 2024/0072772 A1, Feb. 29, 2024
Int. Cl. H03K 3/012 (2006.01); G06F 1/10 (2006.01); H03K 5/14 (2014.01); H03L 7/081 (2006.01); H03K 5/00 (2006.01)
CPC H03K 3/012 (2013.01) [G06F 1/10 (2013.01); H03K 5/14 (2013.01); H03L 7/0812 (2013.01); H03K 2005/00019 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An interface device for a semiconductor device, the semiconductor device including a master device and a plurality of slave devices, wherein the master device and the slave devices are stacked up with electric connection to form a three-dimension structure, the interface device comprising:
a master circuit implemented in the master device; and
a slave circuit implemented in each of the slave devices, coupled to the master circuit through a plurality of through silicon vias, the slave circuit comprising:
a first programmable delay line, providing a first adjusting delay amount according to a first adjust signal, and generating a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount;
a first output clock generator, coupled to the first programmable delay line and generating a second clock signal according to the first delayed clock signal; and
a first phase detector, detecting a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information,
wherein the first adjust signal is generated according to the first phase lead or lag information,
wherein the first output clock generator comprises:
a first delay locked loop, coupled to the first programmable delay line and delaying a phase of the first delayed clock signal to generate a first signal;
a first clock tree circuit, coupled to the first delay locked loop and generating a first sampling signal according to the first signal;
a delay matching circuit, coupled to the programmable delay line and providing a matching delay amount to delay the first delayed clock signal to generate a second signal; and
a second clock tree circuit, coupled to the delay matching circuit and generating the second clock signal according to the second signal.