US 12,283,955 B1
Majority or minority based low power checkerboard carry save multiplier with inverted multiplier cells
Amrita Mathuriya, Portland, OR (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); Rafael Rios, Austin, TX (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Sep. 10, 2021, as Appl. No. 17/472,498.
Application 17/472,498 is a continuation of application No. 17/465,784, filed on Sep. 2, 2021.
Int. Cl. H03K 19/23 (2006.01); H01L 49/02 (2006.01); H10N 30/853 (2023.01)
CPC H03K 19/23 (2013.01) [H01L 28/55 (2013.01); H01L 28/65 (2013.01); H10N 30/853 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of multiplier inputs;
a plurality of multiplicand inputs; and
a plurality of multiplier cells organized in a checkerboard array, wherein the plurality of multiplier cells is coupled to the plurality of multiplier inputs and the plurality of multiplicand inputs, wherein the checkerboard array comprises at least two different types of multiplier cells including a first type and a second type, wherein the first type includes a first multiplier cell that receives a first set of four inputs, two of which are ANDed to provide a sum input, and wherein the second type includes a second multiplier cell that receives a second set of four inputs, two of which are NANDed to provide an inverse sum input.