US 12,283,953 B2
Inverter including transistors having different threshold voltages and memory cell including the same
Seokhyeong Kang, Pohang-si (KR); Youngchang Choi, Pohang-si (KR); Sunmean Kim, Pohang-si (KR); and Kyongsu Lee, Pohang-si (KR)
Assigned to Postech Research and Business Development Foundation, Gyeonsangbuk-do (KR)
Filed by POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION, Pohang-si (KR)
Filed on Nov. 30, 2022, as Appl. No. 18/060,223.
Claims priority of application No. 10-2021-0168696 (KR), filed on Nov. 30, 2021; and application No. 10-2022-0134349 (KR), filed on Oct. 18, 2022.
Prior Publication US 2023/0170907 A1, Jun. 1, 2023
Int. Cl. H03K 19/094 (2006.01); G11C 11/41 (2006.01); H03K 19/0185 (2006.01); H03K 19/0944 (2006.01)
CPC H03K 19/09425 (2013.01) [G11C 11/41 (2013.01); H03K 19/0185 (2013.01); H03K 19/0944 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An inverter comprising:
a first P-MOS transistor connected between a node receiving a drain voltage and a first path node, and configured to operate based on an input voltage;
a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage, and configured to operate based on the drain voltage;
a second P-MOS transistor connected between the output terminal and a second path node, and configured to operate based on a ground voltage;
a second N-MOS transistor connected between the second path node and a node receiving the ground voltage, and configured to operate based on the input voltage;
a third P-MOS transistor connected between the first path node and the second path node, and configured to operate based on the input voltage; and
a third N-MOS transistor connected between the first path node and the second path node, and configured to operate based on the input voltage,
wherein the first P-MOS transistor has a first threshold voltage,
wherein each of the second P-MOS transistor and the third P-MOS transistor has a second threshold voltage higher than the first threshold voltage,
wherein the second N-MOS transistor has a third threshold voltage, and
wherein each of the first N-MOS transistor and the third N-MOS transistor has a fourth threshold voltage higher than the third threshold voltage.