US 12,283,927 B2
Signal line sense amplifying circuit and integrated circuit capable of calibrating driving strength of MOS transistors
Gi Moon Hong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 12, 2022, as Appl. No. 17/964,442.
Claims priority of application No. 10-2022-0085245 (KR), filed on Jul. 11, 2022.
Prior Publication US 2024/0014790 A1, Jan. 11, 2024
Int. Cl. H03K 17/68 (2006.01); H03F 3/45 (2006.01); H03K 17/687 (2006.01)
CPC H03F 3/45269 (2013.01) [H03K 17/6872 (2013.01); H03F 2200/471 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation; and
a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation,
wherein the signal line sense amplifying circuit includes metal-oxide semiconductor field-effect (MOS) transistors for driving input nodes to which input data and inverted input data are input, is configured to calibrate a driving strength of each of the MOS transistors in the calibration operation, and is configured to generate output data by sensing and amplifying the input data and the inverted input data in the sense amplifying operation performed in a state in which the calibration operation is performed.