US 12,283,922 B2
Manufacturing method for compound semiconductor device
Kozo Makiyama, Kawasaki (JP)
Assigned to Fujitsu Limited, Kawasaki (JP)
Filed by Fujitsu Limited, Kawasaki (JP)
Filed on Oct. 11, 2023, as Appl. No. 18/484,469.
Application 18/484,469 is a division of application No. 16/777,944, filed on Jan. 31, 2020, abandoned.
Claims priority of application No. 2019-19110 (JP), filed on Feb. 5, 2019.
Prior Publication US 2024/0039486 A1, Feb. 1, 2024
Int. Cl. H10D 30/01 (2025.01); H01L 21/02 (2006.01); H03F 1/32 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H01L 21/027 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 23/00 (2006.01); H02M 1/42 (2007.01); H02M 3/335 (2006.01); H10D 62/815 (2025.01)
CPC H03F 3/195 (2013.01) [H01L 21/0254 (2013.01); H03F 1/3205 (2013.01); H03F 1/3241 (2013.01); H03F 3/21 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H01L 21/0217 (2013.01); H01L 21/02175 (2013.01); H01L 21/02211 (2013.01); H01L 21/02266 (2013.01); H01L 21/02274 (2013.01); H01L 21/02378 (2013.01); H01L 21/02458 (2013.01); H01L 21/0262 (2013.01); H01L 21/0273 (2013.01); H01L 21/28575 (2013.01); H01L 21/30621 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13064 (2013.01); H02M 1/4225 (2013.01); H02M 3/33576 (2013.01); H10D 62/8162 (2025.01)] 1 Claim
OG exemplary drawing
 
1. A manufacturing method for a compound semiconductor device, the manufacturing method comprising:
forming a semiconductor laminate structure including an electron transit layer and an electron supply layer that are from the compound semiconductor device;
forming a protective film over semiconductor laminate structure;
forming a first resist pattern having an opening portion between a region where a gate electrode is to be formed and a region where a drain electrode is to be formed over the protective film in such a manner that an end portion of the opening portion on a side of the region where the gate electrode is to be formed is spaced apart by a specific distance from the region where the gate electrode is to be formed;
forming, a first insulating film which has a first internal stress over the protective film inside the opening portion using the first resist pattern as a mask;
forming a source electrode and the drain electrode which are arranged in a first direction above the semiconductor laminate structure;
forming, in the first insulating film, a plurality of slits which extend in the first direction using, as a mask, a second resist pattern having a plurality of opening portions which is formed over the protective film, the first insulating film, the source electrode and the drain electrode; and
forming, above the semiconductor laminate structure, the gate electrode which is arranged in the first direction with the source electrode and the drain electrode.