US 12,283,637 B2
MOS capacitor and fabrication method thereof
Jian-Li Lin, Kaohsiung (TW); Wei-Da Lin, Kaohsiung (TW); Cheng-Guo Chen, Changhua County (TW); Ta-Kang Lo, Taoyuan (TW); Yi-Chuan Chen, Tainan (TW); Huan-Chi Ma, Tainan (TW); Chien-Wen Yu, Kaohsiung (TW); Kuan-Ting Lu, Tainan (TW); and Kuo-Yu Liao, Kaohsiung (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Oct. 31, 2022, as Appl. No. 17/976,888.
Application 17/976,888 is a division of application No. 17/145,416, filed on Jan. 11, 2021, abandoned.
Claims priority of application No. 202011429361.X (CN), filed on Dec. 7, 2020.
Prior Publication US 2023/0048684 A1, Feb. 16, 2023
Int. Cl. H01L 29/94 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/94 (2013.01) [H01L 29/66181 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of forming a metal-oxide-semiconductor (MOS) capacitor, comprising:
providing a substrate comprising a capacitor forming region thereon;
forming an ion well having a first conductivity type in the substrate;
forming a counter doping region having a second conductivity type in the ion well within the capacitor forming region by performing only one implantation step of implanting dopants having the second conductivity type into the ion well with an energy of about 15-25KeV and a dosage of about 1E15-5E15 atoms/cm2; and subjecting the counter doping region and the ion well to a rapid thermal anneal process at a temperature of about 950-1060 degrees Celsius;
forming a capacitor dielectric layer on the ion well within the capacitor forming region;
forming a gate electrode on the capacitor dielectric layer after performing the only one implantation step;
forming a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region;
forming a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region,
wherein the source doping region and the drain doping region are formed by implanting dopants having the second conductivity type after forming the gate electrode,
wherein the second conductivity type is opposite to the first conductivity type,
wherein the source doping region and the drain doping region are spaced apart from the counter doping region after the implantation steps by interposing regions of the ion well having the first conductive type; and
performing an annealing process to activate dopants in the source doping region and the drain doping region,
wherein after performing the annealing process, the counter doping region merges with the source doping region and the drain doping region in the interposing regions of the ion well,
wherein the counter doping region has a junction directly underneath the counter doping region in the ion well that is deeper than a lowest junction of the source doping region or a lowest junction of the drain doping region in the ion well.